library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;


entity CLA is
port( A_in : in  std_logic_vector(3 downto 0);
      B_in : in  std_logic_vector(3 downto 0);
      S_out: out std_logic_vector(3 downto 0);
		C_int: in  std_logic;
      C_out: out std_logic
);
end CLA;

architecture Structural of CLA is

component oneBitFA
port(	 A 	: in 	std_logic;
       B 	: in  std_logic;
       S 	: out std_logic;
       G 	: out std_logic;
       P 	: out std_logic;
       C_in : in  std_logic
);
end component;

component CLAgenerator
port( P 		: in  std_logic_vector(3 downto 0);
      G 		: in  std_logic_vector(3 downto 0);
      C_zero: in  std_logic;
      C 		: out std_logic_vector (4 downto 0)
);
end component;

signal gen : std_logic_vector (3 downto 0) := (others => '0');
signal prop: std_logic_vector (3 downto 0) := (others => '0');
signal carry:std_logic_vector (4 downto 0) := (others => '0');
begin

carry(0) <= C_int;
oneBitFA_0: oneBitFA port map(A_in(0),B_in(0),S_out(0),gen(0),prop(0),carry(0));
oneBitFA_1: oneBitFA port map(A_in(1),B_in(1),S_out(1),gen(1),prop(1),carry(1));
oneBitFA_2: oneBitFA port map(A_in(2),B_in(2),S_out(2),gen(2),prop(2),carry(2));
oneBitFA_3: oneBitFA port map(A_in(3),B_in(3),S_out(3),gen(3),prop(3),carry(3));
generator : CLAgenerator port map (prop,gen,C_int,carry);
C_out <= carry(4);

end Structural;





